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simprim problems on modelsim se
Hello, I'm new to vhdl and synthesis so please forgive me if my questions seem blatantly obvious. I am using xilinx ise 9.1 and modelsim se. I wrote a vhdl model using modelsim and completed the functional simulation with everything working fine. The synthesis, translate, map and place & route...- saiyijinprince
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- Forum: VHDL
