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Conversion program
Here is Mikes solution to the problem which works really well.<br> <br> #!/usr/bin/perl<br> while(<>){<br> if(/^\s*output\s+(.*);\s*$/){<br> print "$1\t: out std_ulogic;\n";<br> }<br> if(/^\s*input.+(..):(..)]\s*(.*);\s*$/){<br> print "$3\t... -
Conversion program
Sorry ,looking at it now that example is awfull. The following is an example of what I need to convert.<br> This=> input [31:24] rgf_bd_addr;<br> input rsm_vld_bit;<br> output r_data; <br> <br> To This=> rgf_bd_addr : in... -
Conversion program
Hi,<br> I am currently writing a program to convert Verilog to VHDL using perl. Does anyone know how to get perl to pull certain words out of a string.<br> EG.<br> std_ulogic anyword [31:24;;<br> <br> I need to pull anyword from the string and write it to a file.<br> Any help would be greatly...
