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wait for
Because I'm acustomed to using a sensitivity list in a process, I used a counter to simulate a delay. Which is the more efficient method for implementing a delay at startup? Thank you for your reply but the problem I was having is figuring out where exactly these statement can be placed. Can... -
wait for
I am making an LCD interface, and for the initialization part, several signals must be delayed over some time. How can I go about incorporating the "wait for" statement so that I can delay the first several signals when initializing? Any help would be greatly appreciated... -
Parallel to Serial Conversion
Forgot to add that the clock (sampleCLKreqIN0 @ 100MHz) is now TWICE the frequency of ImodDATA and QmodDATA (@50MHz). -
Parallel to Serial Conversion
I tinkered with the code a bit more and got the result below which I think is more reasonable, but still not sure if it's the right approach. SER_TO_PAR_AND_OVERSAMP: process(sampleCLKreqIN0, ImodDATA, QmodDATA) begin if (reset = '1') then dataOUT <= (others => '0'); dataIQselect <=... -
Parallel to Serial Conversion
I'm attempting a parallel to serial conversion but i'm having difficulties implementing it. i have two signals (ImodDATA and QmodDATA) 11-bits wide that are concatinated with 3 more bits to yield the desired 14-bit dataOUT output. there are some conditions as described in the code, but the... -
DLL
It synthesized after I removed all the generics from the buffer components. Also, when I made my test bench, I had set the reset signal initially to high for one clock cycle. When I just left the reset signal at low, I was able to get the desired outputs. Weird how the reset prevented the... -
DLL
So I tried to use a DLL for implementing a phase shift (better performance at fanout), but when trying to simulate it using a testbench (in ModelSim XE II 5.7g), it doesn't work. Am I missing something? BTW, I used "XAPP132 DLL 1X and 2X" example from the xilinx home to make the code... -
Phase Shifting
Oh yeah, i don't understand why the else conditions are not valid. Also, the clock_out90 is actually phase shifted with respect to the clock_out signal, not the input clock signal (where both of these signals are half the frequency of the original clock). at least that's what the test bench... -
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Phase Shifting
Just wondering if there's a more efficient way of creating two phase shifted signals which are going to be used later for sampling. Also, is it possible to create a phase shifted signal running at the maximum frequency of the clock? my guess is no, but maybe i'm wrong. here's what i came up... -
BPSK/QPSK implementation in VHDL
Does anyone know how to implement BPSK, QPSK, OQPSK or any other type of modulation in VHDL. Any links to such material would be appreciated. Thanks. -
Basic Problem
oh yeah, and since input is a byte long, you'll have to create a component (if else) and instantiate it into the architecture. -
Basic Problem
try replacing temp with input and taking the variable temp declaration off.
