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The size of the integer is most likely limited by the simulator you are using. You can try using the real type. In modelsim it can be as large as 1.000000e+308. I assume you need the integer for something that you want to look at in a simulation only.

See Ray Andraka's web site

have you tried force -freeze ?

Look at the xilinx application notes for building asynchronous fifos. xapp051.pdf xapp131.pdf xapp258.pdf

'left should work with any size vector (string) if the input string is any length then your function may need a parameter that tells it what size std_logic_vector to return and what to do if the input string is too long or too short.

Post your code and I will look at it.

Post your code and I will look at it?

Are you using the clock that comes with the data to write into the dualport ram/fifo? What is your target technology?

-- 1. If you want a register you need a clock. Unless you have a reason for -- using a latch you probably want to use a register. -- 2. Does your target device have internal 3-state buffers/lines (xilinx)? -- If so, you can have one signal that is an input and an output...

library ieee; use ieee.std_logic_1164.all; entity temp4 is generic(K : positive := 4; N : positive := 3); port (Din : in std_logic_vector(N-1 downto 0); Dout : out std_logic_vector((N*K)-1 downto 0)); end temp4; architecture test of temp4 is begin main ...

(I use modelsim XE so I hope this helps) My guess is that the value of Count1 is not valid at the beginning of simulation time. On my pc using modelsim an unitialized integer is -2147483648. Your array only has values from 1 to 25... For simulation, you can get around this problem in at...

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity temp2 is port (RST : in std_logic; CLK : in std_logic; Bin : in std_logic_vector(3 downto 0)); end temp2; architecture sim of temp2 is --I don't know how to make the std_logic_vector an...

You can use default values for inputs. Sometimes it helps to only have one input per line. entity ALU is port ( A : in BIT_VECTOR(3 downto 0) := 5; B: in BIT_VECTOR(3 downto 0) := 7; OP: in BIT_VECTOR(2 downto 0); CLK: in BIT; F: buffer BIT_VECTOR(3...

I doubt FPGA express can create a divider for you. Can you perform your addition using a shifter (divide by power of 2) and a subtractor?

--this uses a generic to determine the number of stages library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clockdiv2 is generic (DIV : positive := 10); --number of stages > 0 port (Clear : in std_logic; CLK : in std_logic; Dout : out...

--doesn't deal with sign library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity conversion is end conversion; architecture test of conversion is signal one : std_logic_vector(3 downto 0); signal two : real; signal three : integer; begin main ...