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Recent content by yein
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Delay problem
I wonder why i use the clause like: a<=b after 10 ns there is no effect in the timing simulation. why does it like this? Is there any differences in the waveform if using the functional or timing simulation with above clause? I am using quartus 2 web edition. Thanks in advance.. -
help!!! binary to bcd converter
I am successful synthesize the code but the delay is quite large...It's undesirable... IS there any suggestion to revise the code? The cct diagram and also the code with be attached here.. Thank for helping.... LIBRARY ieee; USE ieee.STD_LOGIC_1164.all; USE ieee.STD_LOGIC_ARITH.all; USE... -
help urgent!!! binary to bcd converter
Yes. I'm new to VHDL. Actually i am designing a calculator tht can perform addition, subtraction and multiplication only. User will key in the maximum 2 BCD numbers (56+72, 56*4,...).For addition and subtraction, i can do it in BCD. But for multiplication, I have to convert bcd into binary code... -
help urgent!!! binary to bcd converter
I m curently work out this converter but the compilation is not successful. Below is the codes and error message. And I am using shift add3 algorithm for this. LIBRARY ieee; USE ieee.STD_LOGIC_1164.all; USE ieee.STD_LOGIC_ARITH.all; USE ieee.STD_LOGIC_UNSIGNED.all; ENTITY projectTest3 IS port(...
