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Recent content by vhdlverilog
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Synthesis of constants
Synthesis tool doesnot support that. instead u try this,use a reset signal in u'r entity. and initialise it when reset comes i hope u understood. if (reset='1') then thatsignal<="what ever value" else do the remainig.- vhdlverilog
- Post #2
- Forum: VHDL
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loops in vhdl
i think u'r question is valid. which version of xilix r u using? if u r using trial version, loops r supported but, the statements EXIT,BREAK,NEXT wont work- vhdlverilog
- Post #3
- Forum: VHDL
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Modeling a CLock in VHDL
hai mahal, u just write this code some signal is there of name clk clk<=not(clk) after 5ns. depending on the delay that u keep u'r clock frequency depends on delay dont forget to initialise the signal.- vhdlverilog
- Post #3
- Forum: VHDL
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declaration & assignment
u missed out a semocolon(;) after the assignment to signal a hope u might have got it by now- vhdlverilog
- Post #4
- Forum: VHDL
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Reading from Memory
how did u implement memeory. i guess it is a 2 dimentional array of bit or std_logic then,memory elements are accessed in the same way as the array elements.- vhdlverilog
- Post #2
- Forum: VHDL
