I too am new to VHDL, but probably the following way would help u out...
entity ACC is
generic (Delay: Time := 10 ns)
port ( CLK, RESET: in bit ;
-- bla bla bla
CFLG, ZFLG, NFLG, OFLOW : in Bit --instead of this use
flags_in: in Bit_vector( 7 downto 0); -- and...