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Recent content by sunil287
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declaration & assignment
Hi , You are trying to drive input signals A and B which is not allowed. -
VHDL logic error
Hi, In both the processes , one of the signal that is being driven is included in the sensitivity list. Try removing reg20 from the sensitivity list. And sensitivity list is also not updated properly. Signal rst_conv need to be included in the sensitivity list. -
passing generic value
If you want to pass a generic value to a top level entity, then have a package file where map this generic to a signal type defined in package(appropriate type). Just use work.package.all in the header portion of top level entity and compile that package before this entity.
