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Recent content by stryker213
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4:1 MUX issue
Hello, I'm having some trouble implementing my 4:1 MUX and was hoping I could get some input. My main issue is this, the MUX will need to have an output of 'Z' when EN=0. I coded the following: LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4 IS Port(D: in std_logic_vector(3 downto...- stryker213
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- Replies: 1
- Forum: VHDL
