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Recent content by maxnil
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Hierarchical signal probing in VHDL
Is there any way in VHDL to 'probe' a local signal that is located in a sub block at a lower level in the design hierarchy? In Verilog you can write: assign kalle = top_block.sub_block_a.sub_block_b.signal_x if you whant to 'look' at 'signal_x' that is in 'sub_block_b'.
