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Recent content by JayHandle
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out vs buffer & package vs. components
Hello, Can someone please recommend when to use buffer vs. out mode and when to use packages vs. component instantiation? I'll be working on a reasonably large project with 2 other students, and we need to get the software engineering aspects of VHDL down pat. -james -
Simple Problem: i/o declaration error
I've solved my own problem... The problem was that as the Synopsys simulator traverses the hierarchy, it goes through different entities, and changes its current view of the port names/variables/signals. Therefore, when assigning values, always use the full path name to avoid the... -
Simple Problem: i/o declaration error
Hello, I'm just learning about VHDL components and I'm having a problem with the i/o ports being undeclared in the top level of the hierarchy. Synopsis vhdlan compiles the program perfectly, but vhdldbx (the debugger/simulator) will state that the port names are undeclared the second time I...
