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Recent content by isamel85
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Describe in VHDL a generator parallel 4 bits to serial 1 bit
Hello, I want to describe in VHDL a generator parallel 4 bits to serial 1 bit. Indeed, at each clock edge (250 kHz), we take only one bit starting with the least significant bit (LSB). Example: Input = "0101" (over 4 bits) So at first clock edge, output = '1' (LSB) Second clock edge, output =... -
Digital to analog converter
Hello, Actually I am looking for a digital to analog converter (preferably an evaluation board) in order to connect an FPGA with a RF signal generator N9310A (he plays the role of an I and Q modulator and includes two inputs analog I and Q on rear panel and he can transpose the two analog... -
Sending binary data from Matlab to FPGA using the serial port
Hello, In fact, I'm working on a project which aims to implement a reconfigurable Zigbee tranceiver on XUPV5-LX110T Evaluation platform which integrates a Virtex 5 FPGA. I am currently in the phase of real test, so now I just want to test my transmitter. First, I want to send my binary data from... -
FPGA from / to PC Data
Hello, In fact, I'm working on a project which aims to implement a reconfigurable Zigbee tranceiver on XUPV5-LX110T Evaluation platform which integrates a Virtex 5 FPGA. I am currently in the phase of real test. First, I want to send my data from a PC to FPGA and receive it (to treat my... -
FPGA from / to PC Data
Hello, In fact, I'm working on a project which aims to implement a reconfigurable Zigbee tranceiver on XUPV5-LX110T Evaluation platform which integrates a Virtex 5 FPGA. I am currently in the phase of real test. First, I want to send my data from a PC to FPGA and receive it (to treat my...- isamel85
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