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Recent content by Hasan22
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VHDL
Well ; I need to created a data generator to send packets ( as Start bits,Header,Data,Parity,Checksum,)I use a 50MHZ divided to 4Hz clock ; Can anyone tell me how to star to write this type of a generator please I need to send 1010 as the Start bit and an 8 bit string as the header 24 bit data...
