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Recent content by Flueras
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PROBLEMS with my PC
Hello everybody! I've designed in vhdl a simple 2-phase cl0ck Program Counter(PC) which is described next: in principle my pc should output the sum of either pc + 1, or Pc + literal (taken from Input3 ), or just the literal(Input3) . the clk2 is just after the clk1 signal; and have the same...
