Tek-Tips is the largest IT community on the Internet today!
Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!
-
Congratulations wOOdy-Soft on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!
Recent content by ditt0
-
New to VHDL
Hi all, I'm very new to VHDL n i need some help here. 1) the program sounds like this package abc is subtype counter_type is interger range 0 to ((2**13)-1); constant clock_cycle : counter_type :=8000; this first lines means my value will go from 0 to 8191, but why the second line...
