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Recent content by byadeg
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test bench in VHDL
hi, Can any one help me with this..... What is the equivalent code in a VHDL ( for the purpose of writing a test bench) for this command in the Modelsim command promt.. VSIM>force -freeze /DATA/ 10101100 0 -cancel 50 the DATA here is a INOUT type. I want it to be in the VHDL like this...
