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Implementing Sequential Circuit in Verilog

Implementing Sequential Circuit in Verilog

(OP)
I'm trying to implement the following Sequential Circuit in Verilog (Modelsim 10.4a)



Here's the code I'm using

seq_circuit1.v

CODE

module seq_circuit1(x, clk, Q0, Q1);
 input x, clk;
 output Q0, Q1;
 reg J0,K0,J1,K1;
always @(negedge clk)
begin
 J0 = Q1 & ~x;
 K0 = Q1 & x;
 J1 = x;
 K1 = (Q0 & x) || (~Q0 & ~x);
 jkfflop JKff0 (J0,K0,Q0);
 jkfflop JKff1 (J1,K1,Q1);
end
endmodule 

jkfflop.v

CODE

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
 if(J==0 & K==1)
  begin
   assign Q = 0;
  end
 else if(J==1 & K==0)
  begin
   assign Q = 1;
  end
 else if(J==1 & K==1)
  begin
   assign Q = ~Q;
  end
endmodule 

I'm getting some errors and I'm unable to figure out why. Can anybody tell me where did I do it wrong.

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