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VHDL Counter Problem (Please Help)

VHDL Counter Problem (Please Help)

(OP)
I am not able to do the increment and the testbench for this code.

Question:

A system has a 3-bit input D_IN which is read in at every positive edge of a clock input CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output Count is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the count is reset. When Count reaches 6, the system will assert an output Alarm and the Count will not increase further, till it is reset by giving 0s at D_IN for 3 consecutive cycles.

Test case:

Clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

D_IN 0 0 0 2 4 7 6 0 2 4 6 3 5 7 0 0 0 0
code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity johnson_counter is
port (
D_in : in std_logic_vector(2 downto 0);
alarm : out std_logic;
CLK_I : in std_logic
);
end johnson_counter;

architecture Behavioral of johnson_counter is

signal xnew, xold, count1, count2: unsigned(2 downto 0):=(others => '0');

begin


process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
xnew <= std_logic_vector(unsigned(D_in));
xnew <= xnew - "010";
if (xnew => xold) then
count1 <= count1 + "1";
if(xnew = 0) then
count2 <= count2 + "1";
if(xnew /= 0) then
count2 <= "0";
if(count2 = "011") then
alarm <= "1";
end if;
end if;
end if;
end if;
end if;
end process;

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