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Test Bench for 2 out of 5 code error Help

Test Bench for 2 out of 5 code error Help

(OP)
Hi all !
I'm new to VHDL and i have wrote and compiled the 2 of 5 code error correction. My question here is there a way to add timing delay directly into what i have wrote or i have to write the separate test bench(if so hint on how to write test bench would be great), any help is appreciated. thank you

here is my complied code:

Quote:


--Part 3

library ieee; -- component #1
use ieee.std_logic_1164.all;

entity NAND_GATE is
port ( A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
E: in std_logic;
Y: out std_logic
);
end NAND_GATE;

architecture behv of NAND_GATE is
begin
process(A, B, C, D, E)
begin

if (A='1' and B='1' and C='1' and D='1' and E='1') then
Y <= '0';
else
Y <= '1';
end if;
end process;

end behv;

--------------------------------------------------------
library ieee; -- component #2
use ieee.std_logic_1164.all;

entity NAND1_GATE is
port ( F1: in std_logic;
F2: in std_logic;
F3: in std_logic;
F4: in std_logic;
F5: in std_logic;
F6: in std_logic;
F7: in std_logic;
F8: in std_logic;
F9: in std_logic;
F10: in std_logic;
Y1: out std_logic
);
end NAND1_GATE;

architecture behv of NAND1_GATE is
begin
process(F1, F2, F3, F4, F5, F6, F7, F8, F9, F10)
begin

if (F1='1' and F2='1' and F3='1' and F4='1' and F5='1' and F6='1' and F7='1' and F8='1' and F9='1' and F10='1') then
Y1 <= '0';
else
Y1 <= '1';
end if;
end process;

end behv;

-------------------------------------------------------

library ieee; -- top level input
use ieee.std_logic_1164.all;
use work.all;

entity comb_ckt is

port( input0: in std_logic;
input1: in std_logic;
input2: in std_logic;
input3: in std_logic;
input4: in std_logic;
output: out std_logic
);


end comb_ckt;

architecture struct of comb_ckt is

component NAND_GATE is
port ( A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
E: in std_logic;
Y: out std_logic
);
end component;

component NAND1_GATE is
port ( F1: in std_logic;
F2: in std_logic;
F3: in std_logic;
F4: in std_logic;
F5: in std_logic;
F6: in std_logic;
F7: in std_logic;
F8: in std_logic;
F9: in std_logic;
F10: in std_logic;
Y1: out std_logic
);
end component;

signal wire1: std_logic;
signal wire2: std_logic;
signal wire3: std_logic;
signal wire4: std_logic;
signal wire5: std_logic;
signal wire6: std_logic;
signal wire7: std_logic;
signal wire8: std_logic;
signal wire9: std_logic;
signal wire10: std_logic;

--****************************************************************************************************************************
begin

gate1: NAND_GATE port map (A=>input0 ,B=>input1 ,C=>"NOT"(input2), D=>"NOT"(input3), E=>"NOT"(input4), Y=> wire1 );
gate2: NAND_GATE port map (A=>input0 ,B=>"NOT"(input1) ,C=>input2, D=>"NOT"(input3), E=>"NOT"(input4), Y=> wire2 );
gate3: NAND_GATE port map (A=>"NOT"(input0) ,B=>input1 ,C=>input2, D=>"NOT"(input3), E=>"NOT"(input4), Y=> wire3 );
gate4: NAND_GATE port map (A=>input0 ,B=>"NOT"(input1) ,C=>"NOT"(input2), D=>input3, E=>"NOT"(input4), Y=> wire4 );
gate5: NAND_GATE port map (A=>"NOT"(input0) ,B=>input1 ,C=>"NOT"(input2), D=>input3, E=>"NOT"(input4), Y=> wire5 );
gate6: NAND_GATE port map (A=>"NOT"(input0) ,B=>"NOT"(input1) ,C=>input2, D=>input3, E=>"NOT"(input4), Y=> wire6 );
gate7: NAND_GATE port map (A=>input0 ,B=>"NOT"(input1) ,C=>"NOT"(input2), D=>"NOT"(input3), E=>input4, Y=> wire7 );
gate8: NAND_GATE port map (A=>"NOT"(input0) ,B=>input1 ,C=>"NOT"(input2), D=>"NOT"(input3), E=>input4, Y=> wire8 );
gate9: NAND_GATE port map (A=>"NOT"(input0) ,B=>"NOT"(input1) ,C=>input2, D=>"NOT"(input3), E=>input4, Y=> wire9 );
gate10: NAND_GATE port map (A=>"NOT"(input0) ,B=>"NOT"(input1) ,C=>"NOT"(input2), D=>input3, E=>input4, Y=> wire10 );
gate0: NAND1_GATE port map (F1=>wire1, F2=>wire2, F3=>wire3, F4=>wire4, F5=>wire5, F6=>wire6, F7=>wire7, F8=>wire8, F9=>wire9,F10=>wire10, Y1=>output);

end struct;

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