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Home > Forums > Programmers > Languages > Verilog Forum

Pulse signal - constant frequency, variable working cycle

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56743 (TechnicalUser)

26 Nov 11 15:51

Hello! I need to create a VHDL code for this situation:

Draw a control circuit that generates a pulse signal with:
- fixed working frequency (100 KHz)
- variable working cycle

The phase difference should be increased or decreased by the direction of the spin of a rotary control of 8 bits.

Additional info:
D = t (on) / T

- D = working cycle
- t (on) = Time the activated signal lasts (rotary control of 8 bits)
- T = signal period (constant)

(see the signal in the image attached)

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