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help please!!

help please!!

(OP)
I am a noob when it comes to verilog...the worst there is.
The thing is that i have a project in verilog that involves simulating a simple static ram module.I found the code somewhere on the net but i don't know how it works or rather how can i use it.I maneged to make a .v file and then used the vvp command in verilog 0.93 but nothing happens.
If someone here,with God-like patience could explain me how to use the code/program it will mean the world to me.

The code:

//SRAM Model
module sram(CSB,WRB,ABUS,DATABUS);
  input CSB;             // active low chip select
  input WRB;             // active low write control
  input [11:0] ABUS;     // 12-bit address bus
  inout [7:0] DATABUS;   // 8-bit data bus
                 //** internal signals
  reg  [7:0] DATABUS_driver;
  wire [7:0] DATABUS = DATABUS_driver;
  reg [7:0] ram[0:4095];            // memory cells
  integer i;

  initial     //initialize all RAM cells to 0 at startup
    begin
    DATABUS_driver = 8'bzzzzzzzz;
    for (i=0; i < 4095; i = i + 1)
       ram[i] = 0;
    end

  always @(CSB or WRB or ABUS)
    begin
      if (CSB == 1'b0)
        begin
        if (WRB == 1'b0) //Start: latch Data on rising edge of CSB or WRB
          begin
          DATABUS_driver <= #10 8'bzzzzzzzz;
          @(posedge CSB or posedge WRB);
          $display($time," Writing %m ABUS=%b DATA=%b",ABUS,DATABUS);
          ram[ABUS] = DATABUS;
          end
        if (WRB == 1'b1) //Reading from sram (data becomes valid after 10ns)
          begin
          #10 DATABUS_driver =  ram[ABUS];
          $display($time," Reading %m ABUS=%b DATA=%b",ABUS,DATABUS_driver);
          end
        end
      else //sram unselected, stop driving bus after 10ns
        begin
        DATABUS_driver <=  #10 8'bzzzzzzzz;
        end
    end
endmodule

I hope i didn't offend someone by posting here but i am out of options.
 

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