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compare 2's complement in verilog

compare 2's complement in verilog

(OP)
I am now converting my design to 2's complement, and I am having trouble using the compare operator with the assign command.

wire w7;
assign w7 = (Vout > Vpeak)? 1 : 0;

Vpeak will NEVER go below zero so I was going to write an if statement saying the following:

always @ (Vout or Vpeak)
begin
if(Vout[9])
assign w7 = 0;
else
assign w7 = (Vout > Vpeak)? 1 : 0;
end

With this change I get an error stating "Reference to scalar wire 'w7' is not a legal reg or variable lvalue"

Do you have any advice?
 

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