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Verilog SPI Help - Spartan 3e - Master / Slave config

Verilog SPI Help - Spartan 3e - Master / Slave config

Verilog SPI Help - Spartan 3e - Master / Slave config

(OP)
I'm trying to design a Verilog SPI interface on my Spartan 3e board. I'm having issues creating the Master and Slave SPI design. I'm trying to get two Spartan 3e boards to communicate. All that is required is that they can send 8 bits of data to eachother. Any ideas? Does anyone have any examples?

I created a module which has the name SPI. This module will shift a bit out on the MOSI line every positive edge. After the positive edge has occurred, it will increment a counter and enable a busy register. When ever the counter is incremented, a bit will be received on the MISO line with respect to the positive edge of the counter register. When the counter register has has reached 8, the data out of this module will be updated as well as the data in. Then the transfer via MISO and MOSI starts again.

Do any of you guys have any examples on how to program this SPI scenario? I have made several designs using a 25 MHz clock and it seems that the data is just getting updated continuously causing 8 of my LEDs to be lit at the same time instead of the corresponding bits which are enabled in my register. I only want the LEDs to be updated if there has been a change detected on the inputs.
Thanks.

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