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(without init value) have a constant value of 0 in block

(without init value) have a constant value of 0 in block

(without init value) have a constant value of 0 in block

(OP)
I have the following code:

module deneme(clock,reset,p1,p2,p3,p4,out);

input clock,reset;
input [3:0] p1,p2,p3,p4;
output [5:0] out;

reg cur_state,next_state;
parameter st_add = 1'b0,st_idle = 1'b1;

reg wen;
reg[5:0] din1,din2;
reg[3:0] a1,a2;
wire[5:0] dout1,dout2;
register_file RAM(clock,wen,din1,din2,a1,a2,dout1,dout2);


reg [3:0] add1U,add1D,add2U,add2D;
reg [4:0] add3U,add3D;
wire [4:0] add1res,add2res;
wire [5:0] add3res;


//state diagram
always @(posedge clock or posedge reset)
if(reset)
    cur_state <= st_add;
else
    cur_state <= next_state;

always @*
if(cur_state == st_add)
    next_state <= st_idle;
    
//combinational part
always @*
if(cur_state == st_add)
begin
    wen = 0;
    a1 = 0;
    a2 = 1;
    din1 = add3res;
    din2 = add3res>>4;
    add1U = p1;
    add1D = p2;
    add2U = p3;
    add2D = p4;
    add3U = add1res;
    add3D = add2res;
end    
else
begin
    wen = 0;
    a1 = 0;
    a2 = 0;
    din1 = 0;
    din2 = 0;
    add1U = 0;
    add1D = 0;
    add2U = 0;
    add2D = 0;
    add3U = 0;
    add3D = 0;
end    
    
    
assign add1res = add1U + add1D;
assign add2res = add2U + add2D;
assign add3res = add3U + add3D;
assign out = add3res;

endmodule


----------------------------------------------
And the RAM that I initiated in the code above is:

module register_file (clk,wen,
data_in1,data_in2,
address1,address2,
data_out1,data_out2);

parameter n=6,m=16,addresswidth=4;

input clk,wen;
input [n-1:0] data_in1,data_in2;
input [addresswidth-1:0] address1,address2;
output [n-1:0] data_out1,data_out2;


reg [n-1:0] array[m-1:0];

always @(posedge clk)
begin
if (wen)
begin
array[address1]=data_in1;
array[address2]=data_in2;
end
end

assign data_out1 = array[address1];
assign data_out2 = array[address2];
endmodule

----------------------------------------------------

When I compile this, I get the following warning:

Xst:2404 -  FFs/Latches <array_0<5:0>> (without init value) have a constant value of 0 in block <register_file>.

What can be the cause of this? Thanks is advance

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