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verilog: missing vhdl conv_inverter macro!

verilog: missing vhdl conv_inverter macro!

(OP)
now change VHDL to Verilog.

my first problem:

 reg [511:0] reg512;
 wire [3:0] lowbits<=addres[3:0];

 case (address)
  16'h400x: reg512[lowbits+7:lowbits]<=busdata;



errors:
ERROR:HDLCompilers:109 - "v.v" line 148 Most significant bit operand in part-select of vector reg 'reg512' is illegal
ERROR:HDLCompilers:110 - ".v" line 148 Least significant bit operand in part-select of vector reg 'reg512' is illegal
ERROR:HDLCompilers:44 - "v.v" line 148 Illegal left hand side of blocking assignment


in vhdl using "conv_integer"

 

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