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Help with 5 bit counter with JK Flip Flops

Help with 5 bit counter with JK Flip Flops

(OP)
Hey guys, my teacher asked me to make a 5 bit counter using JK Flip Flops, and he said the counter has to be an inout port. The thing is, I know almost nothing of verilog, just the basics, and I have no idea what's wrong with my code. I searched the web for the circuit, but for some reason my counter only displays "xxxxx"...

Here's the site where I found the circuit:
http://www.play-hookey.com/digital/synchronous_counter.html

Here's my code:

CODE

module FlipFlopJK(J, K, clock, Q);
    input J, K, clock;
    output Q;
    reg Q;
    reg Qm;
    reg Qn;

    always @(posedge clock)
        if (J == 1 && K == 0)
            Qm <= 1;
        else if (J == 0 && K == 1)
            Qm <= 0;
        else if (J == 1 && K == 1)
            Qm <= ~Qm;
    always @(negedge clock)
        Q <= Qm;
endmodule

module Counter(count, clock, signal, reset, enable);

    input clock, signal, reset, enable;
    inout [0:4] count;
    
    wire clock, signal, reset, enable;
    wire [0:4] count;
    wire A, B, C, D, E;
    wire auxC, auxB, auxA;
    
    assign count[0] = A;
    assign count[1] = B;
    assign count[2] = C;
    assign count[3] = D;
    assign count[4] = E;
    
    assign count = (reset) ? 00000 : count;
    
    FlipFlopJK e (1, 1, clock, E);
    FlipFlopJK d (E, E, clock, D);
    and a1 (auxC, E, D);
    FlipFlopJK c (auxC, auxC, clock, C);
    and a2 (auxB, E, D, C);
    FlipFlopJK b (auxB, auxB, clock, B);
    and a3 (auxA, E, D, C, B);
    FlipFlopJK a (auxA, auxA, clock, A);

endmodule

module testBench();

    wire [0:4] count;
    reg clock, reset, enable, signal;

    Counter c (count, clock, signal, reset, enable);    

    initial begin: Init

        // Zera a chave
        clock = 1;
        enable = 0;
        reset = 0;
        signal = 1;
        // Escreve no arquivo .vcd
        $dumpfile("TP2.vcd");//gtkwave
        $dumpvars(0);//gtkwave
        #2 reset = 1;
        #2 reset = 0;
        #2 enable = 1;
        #10 enable = 0;
        #2 $finish;
        
    end

    always begin
        #1 clock = ~clock;
        $display("Time\t Count\t Clock");
        $monitor("%0d\t %b\t %b\t", $time, count, clock);
    end

endmodule

RE: Help with 5 bit counter with JK Flip Flops

In Verilog, all 'reg' types initialize to x.
So, all 5 of your JK outputs start as x, and stay as
x.  You could initialize the Qm reg in all 5 in
your testbench as follows:

CODE

initial {c.e.Qm, c.d.Qm, c.c.Qm, c.b.Qm, c.a.Qm,} = 5'b00000;

The value should not matter: 5'b10101 should be fine too.

Another problem is that you have 2 assigns to each count bit.
Use:

CODE

    assign count = (reset) ? 5'b00000 : {A, B, C, D, E};

and get rid of:

CODE

    assign count[0] = A;
    assign count[1] = B;
    assign count[2] = C;
    assign count[3] = D;
    assign count[4] = E;
    
    assign count = (reset) ? 00000 : count;

RE: Help with 5 bit counter with JK Flip Flops

(OP)
Thank you, although I already handed it to my teacher, I did some ugly stuff, and it wasn't fully functional, but that's past now =]

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