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# multidimensional array help

## multidimensional array help

(OP)
I'm interested in improving how I use multidimensional arrays. I've created an example design below that implements an AND-OR mux by driving all but one of five vectors to 0 (only one of SelA-SelE can assert at a time) and then ORing the five vectors together.

#### CODE

integer i;
reg [63:0] pVal [4:0];

always @(posedge PClk or posedge aReset) begin
if (aReset) begin
for (i=0; i<=4; i=i+1) pVal[i] <= 0;
pValOut <= 0;
end else begin
pVal[0] <= SelA? SigA : 64'b0;
pVal[1] <= SelB? SigB : 64'b0;
pVal[2] <= SelC? SigC : 64'b0;
pVal[3] <= SelD? SigD : 64'b0;
pVal[4] <= SelE? SigE : 64'b0;
pValOut <= pVal[0] | pVal[1] | pVal[2] | pVal[3] | pVal[4];
end
end

Here are my questions:
1) Can the reset assignment be done without a FOR loop? For example, in VHDL, the assignment would be
pVal <= (others => (others => '0'));

2) Can the OR of all of the array elements be done with a FOR loop so I can more easily change the number of elements? The VHDL would look like this:
MyVar := (others => '0');
for i in 0 to 7 loop
MyVar := MyVar or pVal(i);
end loop;
pValOut <= MyVar;

Can I do something similar in Verilog?

Thanks very much.

Craig

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