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The use of the case statement

studuser (TechnicalUser) (OP)
11 Mar 09 6:59
Hi,

I am trying to write a verilog code for simple CPU for one of my assignmnets. The following is the program I have written so far but found that the prgram is not going in to the case statement at all. Can someone help me figure out the mistake please?

Thanks very much.

module cpu(clock, run, mbr_out);
     
    input clock;
    input run;
    output[7:0] mbr_out;
    
    
reg [7:0] pc, ir, mar,mbr ,mbr_r, dreg, mbr_out;
reg fetch, decode, mem_write, ce, ld, ad, sub, store;
wire clock, run;
wire [7:0] mbr_in;

main_mem mm1 (.clock(clock),.add_in(mar),.data_out(mbr_in),.data_in(mbr_out),.rd_wr

(mem_write) );

      

always@ (posedge clock, ld, ad, sub, store, fetch, decode)

if (run)

begin

case ({clock,ld, ad, sub, store, fetch, decode})
   7'b1100000:
    begin
     mbr = mbr_in;
     dreg [3:0] = mbr [3:0];
     ld =0;
    end
    
   7'b1010000:
    begin
    mbr = mbr_in;
    dreg[3:0] = dreg[3:0] + mbr[3:0];
    ad =0;
    end
    
    7'b1001000:
    begin
    mbr = mbr_in;
    dreg = dreg - mbr;
    sub =0;
    end
    
    7'b1000100:
    begin
    mbr = dreg;
    mbr_out = mbr;
    mem_write =1;
    store =0;
    end
    
    7'b1000010:
    begin
    mar =pc;
    mbr_r = mbr;
    pc=pc+1;
    decode =1;
    fetch =0;
    end
    
    7'b1000001:
    begin
    mbr = mbr_in;
    if (mbr_r== mbr)
      fetch = 1;
     else
       begin
       ir[3:0] = mbr[7:4];
         mar[3:0] = mbr[3:0];
          casex (ir)
                 8'bxxxx0001 : ld =1;  // load
                8'bxxxx0010 : ad = 1; // add
                8'bxxxx0011 : sub =1;// subtract
                8'bxxxx0101 : store =1;// store
              endcase
        end
        decode =0;
      end
   
 endcase
 
 end
endmodule

module main_mem (clock, add_in, data_out, data_in, rd_wr, CE);

input [7:0]add_in, data_in;
input CE, clock, rd_wr;
output data_out;
wire [7:0] add_in, data_in;
reg [7:0] data_out;
reg[7:0] membyte[0:16];
wire rd_wr;

initial
begin
pc = 1;
mem_write =0;
mbr =0;
mar =0;
fetch=1;
data_out =0;
mbr_out =0;
membyte[10] = 8'b 00000010; // data 10
membyte[11] = 8'b 00000011; // data 11
membyte[12] = 8'b 00000001;// data 12
membyte[0] =  8'b 00000000;
membyte[1] =  8'b 00011010; // load mem 10
membyte[2] =  8'b 00101011; // add mem 11
membyte[3] =  8'b 01011110; // store mem 14
//membyte[3] = 8'b 00001110; // load mem 14
//membyte[4] = 8'b 00101100; // subtract 12
//membyte[5] = 8'b 00111111; //store in 15

end

always@(posedge clock)
    begin
    if(rd_wr)
    membyte[add_in]= data_in;
    else
    data_out = membyte[add_in];
    end
endmodule


 

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