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Signal xx cannot be synthesized, bad synchronous description

thehell (TechnicalUser) 
22 Nov 07 21:21 
I have written a 4bit ALU with CCR in VHDL, but when I try to obtain the Synthesis Report in Xilinx ISE 9.2i I get this error: line 39: Signal C cannot be synthesized, bad synchronous description. Line 39 is: " PROCESS(s, CLK) IS" CODElibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU4bit is Port ( x : in STD_LOGIC_VECTOR (3 downto 0); y : in STD_LOGIC_VECTOR (3 downto 0); s : in STD_LOGIC_VECTOR (3 downto 0); CLK : in STD_LOGIC; V, N, Z, C : out STD_LOGIC; f : out STD_LOGIC_VECTOR (3 downto 0));  SEV_SEG: out STD_LOGIC_VECTOR (7 downto 1)); end ALU4bit;
architecture Behavioral of ALU4bit is
begin
PROCESS(s, CLK) IS VARIABLE temp, carry: STD_LOGIC_VECTOR(4 DOWNTO 0);  extra bit is for Cout in arithmetic operations VARIABLE A: STD_LOGIC_VECTOR(3 DOWNTO 0) := x; VARIABLE B: STD_LOGIC_VECTOR(3 DOWNTO 0) := y; VARIABLE k, sub: STD_LOGIC := '0'; BEGIN  initialize variables and outputs C <= '0'; V <= '0'; N <= '0'; Z <= '0'; sub := '0'; carry(4 downto 0) := "XXXXX"; IF (CLK = '1' AND CLK'event) THEN CASE s IS
 arithmetic operations: s(3) = 0 WHEN "0000" => temp := ('0' & A);  transfer x to temp WHEN "0001" => temp := ('0' & A)+1;  increment x by 1 WHEN "0010" => temp := ('0' & A)+B;  add y to x WHEN "0011" => temp := ('0' & A)+B+1;  add y and Cin to x WHEN "0100" => B := NOT B; temp := ('0' & A)+ B;  subtract y from x (one's complement subtraction) sub := '1'; WHEN "0101" => B := NOT B; temp := ('0' & A)+ B +1;  subtract y from x and increment (two's complement subtraction) sub := '1'; WHEN "0110" => temp := ('0' & A)  1;  decrement x sub := '1'; WHEN "0111" => temp := ('0' & B);  transfer y to temp
 logical operations: s(3) = 1
WHEN "1000" => temp := NOT ('0' & B);  invert y WHEN "1001" => temp := ('0' & (A NAND B));  logical nand of x and y WHEN "1010" => temp := ('0' & (A NOR B));  logical nor of x and y WHEN "1011" => temp := ('0' & (A XNOR B));  logical xnor of x and y WHEN "1100" => temp := ('0' & (A XOR B));  logical xor of x and y WHEN "1101" => temp := ('0' & (A OR B));  logical or of x and y WHEN "1110" => temp := ('0' & (A AND B));  logical and of x and y WHEN OTHERS => temp := NOT ('0' & A);  invert x END CASE;
 output assignment IF s(3) = '0' THEN  only consider CCR in arithmetic mode  determine negative bit, N IF temp(3) = '1' THEN N <= '1'; END IF;  determine overflow bit, V carry(0) := '0'; for k in 1 to 4 loop carry(k) := (A(k1) AND B(k1)) OR (carry(k1) AND (A(k1) XOR B(k1))); end loop; IF (carry(4) XOR carry (3)) = '1' THEN V <= '1'; END IF;  determine zero bit, Z IF temp(3 downto 0) = "0000" THEN Z <= '1'; END IF;  determine carry bit, C IF ((sub = '1' AND y > x) OR (sub = '0' AND temp(4) = '1')) THEN C <= '1'; END IF;
END IF;  determine output, f
f <= temp(3 downto 0); ELSE  When CLK is low, give garbage output f <= "XXXX"; C <= 'X'; V <= 'X'; N <= 'X'; Z <= 'X'; END IF; END PROCESS; END Behavioral; The code passes the syntax check and the testbench provides the correct waveforms. The Xilinx documentation on this error does help. I tried replacing the nested IF statements with the bottom block of code to determine the state of the CCR but I get more errors. CODEcarry(0) := '0'; for k in 1 to 4 loop carry(k) := (A(k1) AND B(k1)) OR (carry(k1) AND (A(k1) XOR B(k1))); end loop; V <= '1' WHEN (carry(4) XOR carry (3)) = '1' ELSE '0'; N <= '1' WHEN temp(3) = '1' ELSE '0'; Z <= '1' WHEN temp(3 downto 0) = "0000" ELSE '0'; C <= '1' WHEN ((sub = '1' AND y > x) OR (sub = '0' AND temp(4) = '1')) ELSE '0'; Any suggestions are appreciated. edit: I found that removing the clock fixes the error, but i need this program to have a clock. The xilinx doc mentioned something about 'EVENT and IF statements but I didn't understand. http://www.xilinx.com/support/answers/14047.htm 

Hi thehell,
The problem is that you assign signals both in and out of the synchronous part of your design.
If you assign signals (C is not the only one) synchronous in an if statement with a clock (IF (clk'event AND clk='1')), the tools will create a register. It will not know what to create when you assign the same signal asynchronous.
Make sure you use a signal only synchronous or asynchronous and not a combination!
I also saw an error in your understanding of VHDL. In your comments you state: " When CLK is low, give garbage output". This is not true, because the ELSE will be handled when there's no EVENT at the clock. So this will also be done when the clock doesn't generate an event, eventough it can be high!
Hope this helps!
By the way: Give your signals logical names in stead of C, N, Z, etc. It'll make your code much more readible. 

Hello, You cannot use the structure for the synthesis : If (clk'event and clk='1') ..... else ... end if.
Try to design your ALU with If (clk'event and clk='1') .....
end if. If you cannot do, give me the description of ALU. I will help you. Normally, ALU is purely combinatoire. So, this don't need the clock clk.




