In my code I am calling module (STAGE_i) 3 times.
However, I want to instanciate the module only once and multiplex the inputs at different time. How can I achieve this?
I know first I need to  feed the input to a multiplexer then to the module Stage_i. The problem I am having is when I tried to feed the out put from the first stage to the second stage? Also, how do I controll the inputs with time?  Hear is my code

module array_mult(clk, reset,load, x_in,y_in,p,done);

     
    assign row0[2] = x[2] & y[0];  
    assign row0[1] = x[1] & y[0];
    assign row0[0] = x[0] & y[0];
    assign c0 = 3'b000;

    STAGE_i stage0(row0,x,y_bit_i_plus1,y_i,c0,row1,c1);  
         //flop the output from stage0
         always @ (posedge clk)
            begin
              flop_row1 <=row1;
              flop_c1 <= c1;
            end

    STAGE_i stage1 (flop_row1,x,y[2],y[1],flop_c1,row2,c2);
         //flop the output from stage1
         always @ (posedge clk)
            begin
              flop_row2 <= row2;
              flop_c2   <= c2;
           end
 

    STAGE_i stage2 (flop_row2,x,y[3],y[2],flop_c2,row3,c3);
        //flop the output from stae2
        always @ (posedge clk)
           begin
             flop_row3 <= row3;
             flop_c3   <= c3;
           end


    STAGE_n stage3({x[3] & y[3],flop_row3[2:1]},flop_c3,row4[2:0],row4[3]);
       //flop the output from stage3
       always @ (posedge clk)
          begin
            flop_row4 <= row4;
          end

  
always @ (posedge clk)
      if (reset) CurrentState = ST_Ready;
      else       CurrentState = NextState;

always @ (load or CurrentState) begin
      NextState = ST_Ready;
      case (CurrentState)
          ST_Ready : begin
             if (load) NextState = ST_Load;
             else      NextState = ST_Ready;
          end

          ST_Load   :  NextState = ST_Stage1 ;

          ST_Stage1 :  NextState = ST_Stage2 ;

          ST_Stage2 :  NextState = ST_Stage3 ;

          ST_Stage3 :  NextState = ST_Stage4 ;

          ST_Stage4 :  NextState = ST_Done ;

          ST_Done   :  NextState = ST_Ready;
     endcase                
    end

    assign lock = (NextState == ST_Load);
    assign done = (CurrentState == ST_Done);
    assign pre_product = {flop_row4,flop_row3[0],flop_row2[0],flop_row1[0],row0[0]};

always @ (posedge clk)
    if(reset) begin // reset all the registers
              x <= 0;
              y <= 0;
    end
    else if (lock) begin // load all the registers
             x <= x_in;
             y <= y_in;
    end

always @ (posedge clk)
    if(reset)  p <= 0;
    else if (done) p <= pre_product;

endmodule